1. Field of the Invention
The present invention relates to a nonvolatile memory device. More particularly, the present invention relates to a high-density memory device using a carbon nanotube as a vertical electron transport channel.
2. Description of the Related Art
Memory devices using a semiconductor generally include a transistor, which serves as a switch for forming a current path when information is written to or read from a capacitor, and a capacitor, which stores and preserves electrical charges. In order to provide a large-intensity current flow in the transistor, the transistor needs to have a high transconductance (gm) characteristic. Recently, a conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a high transconductance characteristic has been used as a switching device for a semiconductor memory device to satisfy this requirement.
A conventional MOSFET mainly includes a control gate formed of doped polycrystalline silicon and a source and drain region formed of doped crystalline silicon. Under a same voltage condition, the transconductance of the MOSFET is inversely proportional to a channel length and a thickness of a gate oxide layer, but is proportional to a surface mobility, a dielectric constant of the gate oxide layer, and a channel width. Since the surface mobility and the dielectric constant of an oxide layer are predetermined according to material, such as a silicon wafer with an orientation and a silicon oxide layer, a high transconductance can be accomplished by increasing a ratio of the channel width to the channel length or decreasing the thickness of the oxide layer.
A physical size of the conventional MOSFET, however, needs to be reduced in order to manufacture a high-density memory device. Thus, a size of the gate and a size of the source and drain region also need to be reduced, which causes various problems.
For example, when the size of a control gate is reduced, a cross-sectional area of the control gate is reduced, which induces a large electrical resistance in a transistor. Reduction of the sizes of the source and drain region causes the thickness, i.e., junction depth, to be reduced. A reduction in the junction depth induces a large electrical resistance or occurrence of a punch-through phenomenon. The punch-through phenomenon occurs when a depletion layer of a source contacts a depletion layer of a drain due to a decrease in a distance between the source and the drain. Consequently, it is impossible to control a current flow. In addition, size reduction of such a memory device decreases the width of a channel functioning as a current path to below about 30 nm, thereby disturbing the flow of current. As a result of this disturbance, the memory device operates abnormally. Accordingly, the use of a conventional silicon MOSFET is limited in accomplishing a high-density memory device.